1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which reduces ohmic contact between a metal line and a substrate.
2. Background of the Related Art
A related art method for manufacturing a semiconductor device will be described with reference to FIGS. 1a to 1e. 
As shown in FIG. 1a, a chemical vapor deposition (CVD) oxide film 12 is formed on a semiconductor substrate 11. A photoresist 13 is deposited on the CVD oxide film 12 and then patterned by exposure and developing processes to define a contact region.
Subsequently, the CVD oxide film 12 is selectively removed to partially expose a surface of the semiconductor substrate 11 using the patterned photoresist 13 as a mask, so that a contact hole 14 is formed.
As shown in FIG. 1b, the photoresist 13 is removed and then a titanium (Ti) film 15 and a titanium nitride (TiN) film 16 are sequentially formed on an entire surface of the semiconductor substrate 11 including the contact hole 14.
The Ti film 15 is reacted with the semiconductor substrate 11 to form a silicide, which acts as a having low resistance ohmic contact. The TiN film 16 prevents a line layer, formed later in the process, from being diffused into the substrate.
As shown in FIG. 1c, an annealing process is performed in the semiconductor substrate 11 to react silicon (Si) of the semiconductor substrate 11 with Ti of the Ti film 15, so that a silicide film 17 is formed on the interface between the semiconductor substrate 11 and the Ti film 15.
To form a film of C-54 silicide, annealing at temperature of 850° C. or more is required. However, annealing is actually performed at about 700° C. thus forming C-49 silicide. The resistance of C-49 silicide film is roughly 4˜5 times higher than C-54 silicide film.
As shown in FIG. 1d, a first metal layer (not shown) is formed on the entire surface of the semiconductor substrate 11. The first metal layer is planarized by etch back process or chemical mechanical polishing (CMP) process to form a plug 18 in the contact hole 14.
When forming the plug 18, the CVD oxide film 12 is used as an etching end point to perform etch back process or CMP process. The Ti film 15 and the TiN film 16 over the CVD oxide film 12 are selectively removed in the etching process.
As shown in FIG. 1e, a second metal layer is formed, on the plug 18 and the CVD oxide film 12, to be electrically connected with the semiconductor substrate 11 through the plug 18. The second metal layer is then selectively removed to form a metal line 19.
However, the related art method for manufacturing a semiconductor device has several problems.
First, because the annealing process is performed below 850° C., the silicide film of high resistance is formed. Thus, it is difficult to minimize the resistance of the wilicide layer, i.e., to produce a good ohmic contact.
Second, when compared with the Si, Ti reacts quicker with dopants such as P, As, and B causing dopant loss on the interface between the silicide film and the substrate during the annealing process. This dopant loss results in further increase in resistance, i.e., it degrades the quality of the ohmic contact. Also Ti reacts differently with As, P, and B, resulting in different electrical characteristics in N type and P type substrates.
Third, the silicide film degrades at a temperature of about 750° C. or more. It is difficult to perform annealing process into the silicide film at high temperature due to low thermal stability of the silicide film.
Fourth, since the silicide film is formed unevenly, poor contact occurs.
Finally, the TiN, used as a diffusion prevention film, is a crystal having columnar structure. Thus, it is difficult to effectively prevent the line layer from being diffused into the substrate. Particularly, TiN is not appropriate for prevention or barrier film of a line layer such as Cu, which is quickly diffused.